1. Field of the Invention
The present invention relates to a semiconductor memory device having a memory cell array including a plurality of memory cells which store data and including a sense amplifier circuit amplifying a signal read out from a selected memory cell and transmitted through a bit line, and particularly relates to a semiconductor memory device performing a test to measure a threshold voltage of a MOS transistor included in the sense amplifier circuit, and to a test method thereof.
2. Description of Related Art
As capacity of semiconductor memory devices such as a DRAM has recently become large, a large number of memory cells connected to each bit line in a memory cell array have been required, and there arise a performance problem due to an increase in parasitic capacitance and parasitic resistance. As measures against such a problem, a configuration of the memory cell array having a hierarchical structure of bit lines has been proposed (Refer to, for example, Patent References 1 to 4). If such a hierarchical memory cell array is employed, the number of memory cells connected to the bit line can be suppressed by shortening the length of the bit lines and a configuration advantageous for reducing the parasitic capacitance and resistance can be achieved. Further, since the number of memory cells connected to the bit line is reduced, a single-ended sense amplifier circuit can be employed without using a differential sense amplifier circuit, thereby suppressing an increase in circuit scale.    Patent Reference 1: Japanese Patent Publication No. 3521979    Patent Reference 2: Japanese Patent Publication No. 3529534    Patent Reference 3: Published Japanese Translation No. H10-512085    Patent Reference 4: Japanese Patent Application Laid-open No. 2000-57761
Meanwhile, the single-ended sense amplifier circuit is generally configured to connect each bit line to a gate of a MOS transistor as an amplifying element so as to convert its output to a drain current, and thus is susceptible to fluctuation of a threshold voltage of the MOS transistor. For example, when the threshold voltage of the amplifying element of the sense amplifier circuit varies due to fluctuation of manufacturing process or the like, this causes a problem such as a decrease in operating margin. Thus, it is important to previously screen good products by obtaining threshold voltages of amplifying elements in the respective sense amplifier circuits in manufacturing process. To achieve this, an average value of the threshold voltages of the MOS transistors as the amplifying elements may be obtained for a large number of sense amplifier circuits, and it may be determined whether or not an individual threshold voltage of each amplifying element is appropriate with reference to the average value.
When employing the single-ended sense amplifier circuit, there are provided a large number of sense amplifier circuits corresponding to the number of bit lines arranged in the memory cell array. When a large capacity DRAM is tested, an average value of threshold voltages of the amplifying elements needs to be calculated as a reference for variation thereof for the large number of sense amplifier circuits. Even if, for example, the threshold voltages of the amplifying elements are obtained for one or several sense amplifier circuits, an accurate average value cannot be calculated. Meanwhile, when the threshold voltages of the amplifying elements are to be obtained for the large number of sense amplifier circuits, complex configuration and control are required and a practical test is difficult to perform. In this manner, there has been a problem of difficulty in performing the practical test for the DRAM having the large number of single-ended sense amplifier circuits in order to calculate the accurate average value of the threshold voltages of the amplifying elements.